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IJND-1

International Journal of Nano Dimension (Int. J. Nano Dimens.)

Editor-in-Chief: Dr. Khalil Pourshamsian; Director-in-Charge: Dr. Babak Sadeghi

Online ISSN: 2228-5059

Print ISSN: 2008-8868

Publishes Quarterly

Original Article
High-K Dual Metal Gate-Nano Tube (DMG-NT) FETs: A Possible Solution to Mitigate the Effect of Temperature in NT-FETs

This paper provides a possible solution to minimize the effect of temperature on nano-tube (NT) FETs by applying performance enhancers. Here high-k and dual metal gates(DMG) are used as performance boosters. The high-k downgrades the leakage issues and improves the on-state current(Ion), while dual metal gate suppresses the short-channel-effects (SCEs). Simulation results reflect that Ion […]

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Original Article
Conventional vs. junctionless gate-stack DG-MOSFET based CMOS inverter

In this article, the high-k gate dielectric effect on the operation of complementary metal oxide semiconductor (CMOS) inverter build using conventional (CL) double-gate (DG) metal oxide semiconductor field effect transistor (MOSFET) and junctionless (JL) double-gate (DG) MOSFET has been explored. It is found that the improvement in inverter performance is more pronounced in CL-DG-MOSFET based […]

Original Article
High-K dual metal gate-nano tube (DMG-NT) field effect transistors (FETs): A possible solution to diminish the effect of temperature variation

This paper provides a possible solution to minimize the effect of temperature on nano-tube (NT) FETs by applying performance  enhancers. Here high-k and dual metal gates (DMG) are used as performance boosters. The high-k downgrades the leakage issues and improves the on-state current (Ion), while dual metal gate suppresses the short-channel-effects (SCE). Simulation results reflect […]

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