<?xml version="1.0" encoding="UTF-8"?><!DOCTYPE ArticleSet PUBLIC "-//NLM//DTD PubMed 2.7//EN" "https://dtd.nlm.nih.gov/ncbi/pubmed/in/PubMed.dtd">
<ArticleSet>
		<Article>
		<Journal>
			<PublisherName>International Journal of Nano Dimension (Int. J. Nano Dimens.)</PublisherName>
			<JournalTitle>Representation of a nanoscale heterostructure dual material gate JL-FET with NDR characteristics</JournalTitle>
			<Issn></Issn>
			<Volume>Volume 11 (2020)</Volume>
			<Issue>Issue 1, January 2020</Issue>
			<PubDate PubStatus="epublish">
                <Year>2024</Year>
                <Month>02</Month>
                <Day>07</Day>
			</PubDate>
		</Journal>
		<ArticleTitle>Representation of a nanoscale heterostructure dual material gate JL-FET with NDR characteristics</ArticleTitle>
		<VernacularTitle></VernacularTitle>
		<FirstPage></FirstPage>
		<LastPage></LastPage>
		<ELocationID EIdType="doi"></ELocationID>
		<Language>EN</Language>
		<AuthorList>
            			<Author>
                				<FirstName>Amirreza</FirstName>
				<LastName>Bozorgi Golafzani</LastName>
				<Affiliation>Department of Electrical Engineering, Rasht Branch, Islamic Azad University, Rasht, Iran.</Affiliation>
				<Identifier Source="ORCID"></Identifier>
			</Author>
            			<Author>
                				<FirstName>Seyed</FirstName>
				<LastName>Ali Sedigh Ziabari</LastName>
				<Affiliation>Department of Electrical Engineering, Rasht Branch, Islamic Azad University, Rasht, Iran.</Affiliation>
				<Identifier Source="ORCID">0000-0003-2048-6602</Identifier>
			</Author>
            		</AuthorList>
		<PublicationType>Journal Article</PublicationType>
		<History>
			<PubDate PubStatus="received">
				<Year>2024</Year>
				<Month>02</Month>
				<Day>07</Day>
			</PubDate>
		</History>
		<Abstract>In this paper, we propose a new heterostructure dual material gate junctionless field-effect transistor (H-DMG-JLFET), with negative differential resistance (NDR) characteristic. The drain and channel material are silicon and source material is germanium. The gate electrode near the source is larger. A dual gate material technique is used to achieve upward band bending in order to access n-i-p-n structure which is caused by workfunction difference between electrodes and silicon. In JL-FETs as gate voltage increases, the electric-field intensifies and the band diagram profile starts to change. It is illustrated that, by increasing the gate voltage, the potential barrier decrease and the drain current increase. In the gate voltage of 0.64 V, due to appearance of a negative peak of electric-field and carriers transport within the field, the drain current decrease. Consequently, the NDR characteristic is achieved. With increase of the gate voltage the negative peak of electric-field is intensified and the drain current is decreased.</Abstract>
		<ObjectList>
            			<Object Type="keyword">
				<Param Name="value">Heterostructure</Param>
			</Object>
						<Object Type="keyword">
				<Param Name="value">Junctionless Field Effect Transistor (H-DMG-JLFET)</Param>
			</Object>
						<Object Type="keyword">
				<Param Name="value">Negative Differential Resistance (NDR)</Param>
			</Object>
						<Object Type="keyword">
				<Param Name="value">Workfunction</Param>
			</Object>
						<Object Type="keyword">
				<Param Name="value">Dual Material Gate</Param>
			</Object>
					</ObjectList>
	</Article>
	</ArticleSet>
