<?xml version="1.0" encoding="UTF-8"?><!DOCTYPE ArticleSet PUBLIC "-//NLM//DTD PubMed 2.7//EN" "https://dtd.nlm.nih.gov/ncbi/pubmed/in/PubMed.dtd">
<ArticleSet>
		<Article>
		<Journal>
			<PublisherName>Majlesi Journal of Electrical Engineering</PublisherName>
			<JournalTitle>A New Low Power, Area Efficient 4-bit Carry Look Ahead Adder in CNFET Technology</JournalTitle>
			<Issn></Issn>
			<Volume>Volume 16 (2022)</Volume>
			<Issue>Issue 1, March 2022</Issue>
			<PubDate PubStatus="epublish">
                <Year>2024</Year>
                <Month>02</Month>
                <Day>11</Day>
			</PubDate>
		</Journal>
		<ArticleTitle>A New Low Power, Area Efficient 4-bit Carry Look Ahead Adder in CNFET Technology</ArticleTitle>
		<VernacularTitle></VernacularTitle>
		<FirstPage></FirstPage>
		<LastPage></LastPage>
		<ELocationID EIdType="doi">10.52547/mjee.16.1.65</ELocationID>
		<Language>EN</Language>
		<AuthorList>
            			<Author>
                				<FirstName>Ali</FirstName>
				<LastName>Ghorbani</LastName>
				<Affiliation>Faculty of Computer Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran.</Affiliation>
				<Identifier Source="ORCID"></Identifier>
			</Author>
            			<Author>
                				<FirstName>Mehdi</FirstName>
				<LastName>Dolatshahi</LastName>
				<Affiliation>Department of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran.</Affiliation>
				<Identifier Source="ORCID"></Identifier>
			</Author>
            			<Author>
                				<FirstName>S.</FirstName>
				<LastName>Mohammadali Zanjani</LastName>
				<Affiliation>Big Data Research Center, Najafabad Branch, Islamic Azad University, Najafabad, Iran.</Affiliation>
				<Identifier Source="ORCID">0000-0001-5329-4899</Identifier>
			</Author>
            			<Author>
                				<FirstName>Behrang</FirstName>
				<LastName>Barekatain</LastName>
				<Affiliation>Smart Microgrid Research Center, Najafabad Branch, Islamic Azad University, Najafabad, Iran.</Affiliation>
				<Identifier Source="ORCID"></Identifier>
			</Author>
            		</AuthorList>
		<PublicationType>Journal Article</PublicationType>
		<History>
			<PubDate PubStatus="received">
				<Year>2024</Year>
				<Month>02</Month>
				<Day>11</Day>
			</PubDate>
		</History>
		<Abstract>In this paper, a new hybrid low-power and area efficient Carry Look-Ahead Adder in CNFET technology based on the full-swing Gate Diffusion Input (GDI) technique is proposed. The proposed CLA design in GDI logic style, not only decreases the circuit area effectively but also decreases the power consumption and delay parameters as well. The proposed design is simulated in HSPICE using the CNFET model parameters. Finally, the simulation results justify a good improvement in the circuit performance parameters such as power consumption, delay, chip size area and power-delay product (PDP) for the proposed CLA circuit.</Abstract>
		<ObjectList>
            			<Object Type="keyword">
				<Param Name="value">Carry Look-Ahead Adder</Param>
			</Object>
						<Object Type="keyword">
				<Param Name="value">GDI</Param>
			</Object>
						<Object Type="keyword">
				<Param Name="value">CNFET</Param>
			</Object>
						<Object Type="keyword">
				<Param Name="value">Area-efficient.</Param>
			</Object>
						<Object Type="keyword">
				<Param Name="value">Low-power</Param>
			</Object>
					</ObjectList>
	</Article>
	</ArticleSet>
