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<ArticleSet>
		<Article>
		<Journal>
			<PublisherName>Majlesi Journal of Electrical Engineering</PublisherName>
			<JournalTitle>Asymmetrical Modular Multilevel Converter (A-MMC) with Mixed Cell Sub-Modules (SM) for Improved DC Fault Blocking Capability and Reduced Component Count</JournalTitle>
			<Issn></Issn>
			<Volume>Volume 17 (2023)</Volume>
			<Issue>Issue 1, March 2023</Issue>
			<PubDate PubStatus="epublish">
                <Year>2024</Year>
                <Month>02</Month>
                <Day>03</Day>
			</PubDate>
		</Journal>
		<ArticleTitle>Asymmetrical Modular Multilevel Converter (A-MMC) with Mixed Cell Sub-Modules (SM) for Improved DC Fault Blocking Capability and Reduced Component Count</ArticleTitle>
		<VernacularTitle></VernacularTitle>
		<FirstPage></FirstPage>
		<LastPage></LastPage>
		<ELocationID EIdType="doi">10.30486/mjee.2023.1970275.0</ELocationID>
		<Language>EN</Language>
		<AuthorList>
            			<Author>
                				<FirstName>Himanshu</FirstName>
				<LastName>N Chaudhari</LastName>
				<Affiliation>Electrical Engineering Department, SVNIT, Surat, India</Affiliation>
				<Identifier Source="ORCID">0000-0002-8709-9415</Identifier>
			</Author>
            			<Author>
                				<FirstName>Pranav</FirstName>
				<LastName>B Darji</LastName>
				<Affiliation>Electrical Engineering Department, SVNIT, Surat, India</Affiliation>
				<Identifier Source="ORCID">0000-0002-9685-614X</Identifier>
			</Author>
            		</AuthorList>
		<PublicationType>Journal Article</PublicationType>
		<History>
			<PubDate PubStatus="received">
				<Year>2024</Year>
				<Month>02</Month>
				<Day>03</Day>
			</PubDate>
		</History>
		<Abstract>In this article, asymmetrical modular multilevel converter (A-MMC) topology using mixed cell (SM) with DC-side fault blocking capability and the reduced component count is proposed. The mixed cell submodule is made up of a full-bridge (FB-SM) and a half-bridge (HB-SM) with asymmetric capacitor voltage based on geometric propagation (GP) ratio. Each mixed cell submodule can generate a maximum of four output voltage levels with binary GP ratio and five output voltage levels with ternary GP ratio using six controlled switches and two asymmetric capacitors. The proposed A-MMC topology requires nearly half the number of components and voltage sensors compared to conventional topologies. This will result in simpler control structure of A-MMC with DC fault blocking capability. A voltage balancing algorithm based on normalization is used for capacitor voltage balancing and a hybrid pulse width modulation (H-PWM) technique to generate gating signals. Detailed operational concepts of the proposed topology, the pre-charging process of a capacitor, and performance with different modulation indexes are discussed in length. A detailed simulation model of A-MMC under different operating conditions is carried out using MATLAB/SIMULINK environment. To show the benefits of mixed cell SM, a comparison between the proposed mixed cell and other existing cells is presented in detail. The simulation results analysis show effectiveness of proposed schemes over other schemes presented in literature.</Abstract>
		<ObjectList>
            			<Object Type="keyword">
				<Param Name="value">Reduced Component Count. DC Fault Blocking Capability</Param>
			</Object>
						<Object Type="keyword">
				<Param Name="value">Asymmetrical Modular Multilevel Converter (A-MMC)</Param>
			</Object>
						<Object Type="keyword">
				<Param Name="value">HVDC system</Param>
			</Object>
						<Object Type="keyword">
				<Param Name="value">Mixed Cell</Param>
			</Object>
						<Object Type="keyword">
				<Param Name="value">Hybrid modulation technique</Param>
			</Object>
					</ObjectList>
	</Article>
	</ArticleSet>
