<?xml version="1.0" encoding="UTF-8"?><!DOCTYPE ArticleSet PUBLIC "-//NLM//DTD PubMed 2.7//EN" "https://dtd.nlm.nih.gov/ncbi/pubmed/in/PubMed.dtd">
<ArticleSet>
		<Article>
		<Journal>
			<PublisherName>Majlesi Journal of Electrical Engineering</PublisherName>
			<JournalTitle>Performance Optimization of Broadwell-Y Shaped Transistor Using Artificial Neural Network and Moth-Flame Optimization Technique</JournalTitle>
			<Issn></Issn>
			<Volume>Volume 12 (2018)</Volume>
			<Issue>Issue 1, March 2018</Issue>
			<PubDate PubStatus="epublish">
                <Year>2024</Year>
                <Month>02</Month>
                <Day>15</Day>
			</PubDate>
		</Journal>
		<ArticleTitle>Performance Optimization of Broadwell-Y Shaped Transistor Using Artificial Neural Network and Moth-Flame Optimization Technique</ArticleTitle>
		<VernacularTitle></VernacularTitle>
		<FirstPage></FirstPage>
		<LastPage></LastPage>
		<ELocationID EIdType="doi"></ELocationID>
		<Language>EN</Language>
		<AuthorList>
            			<Author>
                				<FirstName>Navneet</FirstName>
				<LastName>Kaur</LastName>
				<Affiliation>I. K. Gujral Punjab Technical University, Jalandhar, Punjab, India</Affiliation>
				<Identifier Source="ORCID"></Identifier>
			</Author>
            			<Author>
                				<FirstName>Munish</FirstName>
				<LastName>Rattan</LastName>
				<Affiliation>Guru Nanak Dev Engineering College, Ludhiana, Punjab, India</Affiliation>
				<Identifier Source="ORCID"></Identifier>
			</Author>
            			<Author>
                				<FirstName>Sandeep</FirstName>
				<LastName>Gill</LastName>
				<Affiliation>Guru Nanak Dev Engineering College, Ludhiana, Punjab, India</Affiliation>
				<Identifier Source="ORCID"></Identifier>
			</Author>
            		</AuthorList>
		<PublicationType>Journal Article</PublicationType>
		<History>
			<PubDate PubStatus="received">
				<Year>2024</Year>
				<Month>02</Month>
				<Day>15</Day>
			</PubDate>
		</History>
		<Abstract>FinFETs are the emerging 3D-transistor structures due to strong electrostatic control of active channel by gate from more than one side which was not possible in conventional transistor. FinFET structures with rectangular and trapezoidal shape have been excessively analyzed in literature. In this work, FinFET with Broadwell-Y shape proposed by Intel, has been designed and simulated in Technology Computer Aided Design (TCAD). The performance of the designed device was optimized using Moth Flame Optimization (MFO) after the network was trained through Artificial Neural Network (ANN). Results obtained from MATLAB were in close agreement with those obtained from TCAD simulations. Output parameters like leakage current (IOFF) of 2.407e-12, On-Off current ratio (ION/IOFF) of 4.5e06, Subthreshold Swing (SS) of 65.4mV/dec and Drain Induced Barrier Lowering (DIBL) of 37.9mV/V were obtained after optimization. Short channel effects are improved for 20nm gate length as SS is close to ideal value 60mV/dec and DIBL is below 100mV/V which makes this designed structure a good option for nanoscale applications.</Abstract>
		<ObjectList>
            			<Object Type="keyword">
				<Param Name="value">FinFET</Param>
			</Object>
						<Object Type="keyword">
				<Param Name="value">Moth-Flame Optimization (MFO)</Param>
			</Object>
						<Object Type="keyword">
				<Param Name="value">Artificial Neural Network (ANN)</Param>
			</Object>
						<Object Type="keyword">
				<Param Name="value">Drain Induced Barrier Lowering (DIBL)</Param>
			</Object>
						<Object Type="keyword">
				<Param Name="value">Subthreshold Swing (SS). Leakage Current</Param>
			</Object>
						<Object Type="keyword">
				<Param Name="value">TCAD</Param>
			</Object>
					</ObjectList>
	</Article>
	</ArticleSet>
