TY - EJOUR
PY - 2024
DA - February
TI - VCO Design and Simulation Using TSMC 0.18 m Process to Meet IEEE802.11a Requirements
T2 - Majlesi Journal of Electrical Engineering
VL - 2
L1 - https://old.oiccpress.com/Majlesi-Journal-of-Electrical-Engineering/article/vco-design-and-simulation-using-tsmc-0-18-%ef%81%adm-process-to-meet-ieee802-11a-requirements/
DO - 10.1234/mjee.v2i2.56
N2 - A complimentary topology is used incorporating TSMC 0.18 mm process to design a CMOS VCO with the center frequency of 5.4 GHz. Simulation results showed tuning range of 13%. The phase noise at 1 MHz offset was measured to be -118.7 dBc/Hz. The VCO core power consumption was 3.3 mW when the power supply voltage was set to 1.5 V. Simulation results verified that the designed structure meets the IEEE802.11a requirements.
IS - 2
PB - OICC Press
KW - CMOS., VCO, en, phase noise, tuning range. IEEE802.11a 
EN -